1. Field of the Invention
The present invention relates to a memory card having a memory device on which a data write operation, a data read operation, and a data erase operation are performed in response to an access from a host apparatus, and also relates to the host apparatus. For example, the present invention relates to timing adjustment for a bus interface that connects the memory card and the host apparatus together.
2. Description of the Related Art
Memory cards such as SD memory cards, which are one type of removable memory devices, have often been used in various portable electronic apparatuses such as personal computers, PDAs, cameras, and cellular phones (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-196613). The SD memory card is able to transfer data at a maximum of 25 MB/sec owing to an expanded high speed mode. However, next-generation memory cards are desired to have a transfer ability equivalent to at least 50 MB/sec.
However, with bus interfaces used in memory cards and based on the current scheme, it is difficult to control operation timings owing to a variation in delay. This in turn makes it difficult to increase the frequency of clock signals used to synchronize operations. The timing and element properties depend on the implementations and combination of the memory card and a host system. This makes it impossible to pre-calculate a predetermined delay value. In this respect, the memory card is different from onboard DRAMs (Dynamic Random Access Memories) and the like.